An essential function in a receiver of digital communication systems is the recovery of a clock signal needed for sampling a received data signal to recover the transmitted data. Typically, this clock recovery function has been obtained by employing a phase locked loop. Phase locked loops include a voltage variable frequency oscillator and a circuit for holding a frequency control voltage. In response to transitions of the received data signal, the phase locked loop corrects the frequency of the voltage variable oscillator and generates the clock signal used to sample the received data signal.
In certain systems data is transmitted using a so-called non-return to zero (NRZ) data system. The NRZ data stream may have long intervals during which there are no data transitions. In the absence of data transitions, the phase locked loop variable oscillator free runs at the last frequency established by the control voltage of the hold circuit. Because of instabilities in the variable frequency oscillator and the hold circuit, the phase of the oscillator drifts and errors result in the data recovery process. Consequently, in systems using phase locked loops for clock signal recovery the interval between data transitions must be restricted in order to minimize the phase drift and, hence, errors in the data recovery.
A further problem with phase locked loops is the need to use the variable frequency oscillator. In many systems this is an added expense.